The present invention relates to electronic apparatuses, control circuits for electronic apparatuses, and methods of controlling electronic apparatuses, and more particularly to an electronic apparatus, a control circuit for an electronic apparatus, and a method of controlling an electronic apparatus that change different states by a predetermined input operation.
Recently, a SUSPEND/RESUME function has been applied to an electronic apparatus such as a personal computer as a part of power management.
The SUSPEND/RESUME function is a sort of power-saving function of a personal computer. According to the SUSPEND/RESUME function, the system of a personal computer is caused to stop an operation of a hard disk or a CPU by operating a SUSPEND/RESUME button so as to change the state of the personal computer to a low power consumption state, and is caused to resume the operation of the hard disk or the CPU by operating the SUSPEND/RESUME button again.
A standard called ACPI (Advanced Configuration and Power Management Interface) is established for the power management of a power-saving function such as this SUSPEND/RESUME function of a personal computer. The power management of a personal computer is usually based on the ACPI standard.
Under the ACPI standard, it is required to have a function enabling a shut-off of power other than the SUSPEND/RESUME function.
Some chip sets house power management functions conforming to the ACPI standard so that the power management function conforming to the ACPI standard can be easily mounted.
FIG. 1 is a block diagram of a conventional electronic apparatus.
A conventional electronic apparatus 1 includes a chip set 2 connected to a SUSPEND/RESUME button 3. The chip set 2 causes an interrupt for a SUSPEND or RESUME operation to a processing part 4 based on an operation of the SUSPEND/RESUME button 3. After performing an operation such as a save of data in process in accordance with the interrupt for a SUSPEND or RESUME operation caused by the chip set 2, the processing part 4 controls a power control part 5 connected to the chip set 2 via the chip set 2 to stop a hard disk or a CPU so that power is supplied to a minimum essential part such as a part for data retention.
The SUSPEND/RESUME button 3 has its one end grounded and the other end connected to the chip set 2. A constant voltage Vc is applied via a resistor R between the SUSPEND/RESUME button 3 and the chip set 2.
If the SUSPEND/RESUME button 3 is switched OFF, the constant voltage Vc is applied to the chip set 2 via the resistor R. Therefore, a SUSPEND/RESUME control terminal Tc of the chip set 2, to which terminal the SUSPEND/RESUME button 3 is connected, is set to a HIGH level.
If the SUSPEND/RESUME button 3 is switched ON, the constant voltage Vc is applied to a ground through the resistor R and the SUSPEND/RESUME button 3. Therefore, the SUSPEND/RESUME control terminal Tc of the chip set 2, to which terminal the SUSPEND/RESUME button 3 is connected, is set to a LOW level.
The chip set 2 monitors a change in the level of the SUSPEND/RESUME terminal Tc. If the level of the SUSPEND/RESUME terminal Tc changes from the HIGH level to the LOW level while the processing part 4 is in a normal operating state, the chip set 2 causes an interrupt for a SUSPEND operation to the processing part 4. When the chip set 2 causes the interrupt for the SUSPEND operation to the processing part 4, the processing part 4 controls operations to be set in a SUSPEND state after saving the data in process.
If the level of the SUSPEND/RESUME terminal Tc changes again from the HIGH level to the LOW level while the processing part 4 is in the SUSPEND state, the chip set 2 causes an interrupt for a RESUME operation to the processing part 4. When the chip set 2 causes the interrupt for the RESUME operation to the processing part 4, the processing part 4 returns the saved data to return to the normal operating state.
Further, the chip set 2 is provided with a function enabling a shut-off of power by the operation of the SUSPEND/RESUME button 3. The chip set 2 monitors the level change of the SUSPEND/RESUME control terminal Tc. If the level of the SUSPEND/RESUME control terminal Tc is maintained at the LOW level, that is, the SUSPEND/RESUME button 3 is maintained in a pressed state, for a predetermined period of time, for instance, four seconds, the chip set 2 directly controls the power control part 5 to shut off the power irrespective of the states of the processing part 4.
FIG. 2 is a waveform chart of an operation of the conventional electronic apparatus. FIG. 2(A) shows a signal supplied to the SUSPEND/RESUME control terminal Tc of the chip set 2 by the operation of the SUSPEND/RESUME button 3, FIG. 2(B) shows the SUSPEND state, and FIG. 2(C) shows a POWER SHUT-OFF state.
If the SUSPEND/RESUME button 3 is operated at a time t0, the SUSPEND/RESUME control terminal Tc of the chip set 2 changes from the high level to the low level as shown in FIG. 2(A).
When detecting the level change of the SUSPEND/RESUME control terminal Tc from the HIGH level to the LOW level, the chip set 2 causes an interrupt for the SUSPEND operation to the processing part 4. When interrupted by the chip set 2, the processing part 4 returnably saves data in process, and then controls the power control part 5 via the chip set 2 so as to shut off the power supply to a predetermined part. Thus, the processing part 4 is set in the SUSPEND state as shown in FIG. 2(B).
Further, the chip set 2 houses a timer. When the level change of the SUSPEND/RESUME control terminal Tc from the HIGH level to the LOW level is detected, the timer housed in the chip set 2 is activated to count time while the SUSPEND/RESUME button 3 is in the pressed state, that is, while the SUSPEND/RESUME control terminal Tc of the chip set 2 is maintained at the LOW level as indicated by a solid line in FIG. 2(A). When the timer counts time until a time t1 at which a predetermined period T0, for instance, four seconds, passes, the chip set 2 controls the power control part 5 to command a so-called POWER SHUT-OFF operation that shuts off all the power.
If pressing the SUSPEND/RESUME button 3 ends at a time t2 at which the predetermined period T0, for instance, four seconds, does not pass while the timer counts time, the chip set 2 maintains the system of the processing part 4 in the SUSPEND state.
Next, if the SUSPEND/RESUME button 3 is pressed at a time t3 so that the level of the SUSPEND/RESUME control terminal Tc of the chip set 2 changes again from the HIGH level to the LOW level as indicated by a broken line in FIG. 2(A), the chip set 2 causes an interrupt for the RESUME operation to the processing part 4. The processing part 4, based on the interrupt for the RESUME operation, controls the power control part 5 via the chip set 2 to turn on the power, and by returning the data saved at the time of the SUSPEND state, enables a processing operation to be resumed from a state before the SUSPEND state.
As described above, the chip set 2 houses a function performing the SUSPEND or RESUME operation, or the POWER SHUT-OFF operation depending on a pressing time of the SUSPEND/RESUME button 3.
However, in the POWER SHUT-OFF operation employing the conventional SUSPEND/RESUME button 3, the power is shut off by pressing the SUSPEND/RESUME button 3 for the predetermined period (four seconds). On the other hand, in the SUSPEND or RESUME operation by pressing the SUSPEND/RESUME button 3, it takes time in saving or returning data so that the SUSPEND or RESUME state is prevented from being set immediately after the operation of the SUSPEND/RESUME button 3. Therefore, in starting the SUSPEND or RESUME operation, the SUSPEND/RESUME button 3 is prone to be pressed for a longer period than necessary.
Therefore, if a user keeps pressing the SUSPEND/RESUME button 3 for a longer period than necessary in starting the SUSPEND or RESUME operation since it takes time in activating the SUSPEND/RESUME function, the power is shut off to erase the data in process, thus causing a problem.
The present invention is made in the light of the above-described point, and has an object of providing an electronic apparatus, a control circuit for an electronic apparatus, and a method of controlling an electronic apparatus which can prevent the transition of states due to an unintentional operation.
The present invention, which is an electronic apparatus changing states thereof based on a predetermined input operation, is characterized by including: input means for performing the predetermined input operation; input operation detection means for detecting a presence or absence of the predetermined input operation to the input means; state transition control means for changing a state of the apparatus from a first state to a second state when the input operation detection means detects an operation of the input means, and changing the state of the apparatus to a third state when a continuation of the operation of the input means for a predetermined period or longer is detected, the first, second, and third states being different from one another; and nullification means for nullifying the operation of the input means before a passage of the predetermined period.
Further, the present invention is characterized in that the input operation detection means includes detection signal generation means for generating a detection signal of a certain state based on the operation of the input means, and that the nullification means includes detection signal restriction means for restricting a period of the certain state of the detection signal within the predetermined period.
According to the present invention, by restricting the period of the predetermined input operation by the input means within the predetermined period, the state of the apparatus is prevented from being changed from the first state to the second state even if the input means is operated for the predetermined period or longer. Therefore, an unnecessary state transition can be prevented, thus increasing the operability of the electronic apparatus.